This invention relates to a redundant clock system.
In synchronous digital multiplex data systems it is common to provide a redundant clock and data bus distribution for reliable operation. The clock busses are referred to as the active and standby busses with the clock signal of the active bus derived from a primary clock reference and the standby clock signal phase locked to that of the active bus clock signal rather than its own associated primary clock reference. During switchover, when the alternate primary clock reference is selected as the source for the active bus phase, discontinuity will occur between the redundant clock busses which can cause system timing errors.
Other important features that may be required of a redundant clock bus distribution plan for some data systems may include active and standby clock precision phase alignment and duty factor correction. Duty factor correction is applied when it is required that the active and standby clocks be maintained at a specific duty factor regardless of the duty factor tolerance of the master/standby clock references.
A redundant clock system for providing bit and frame clock signals is disclosed in U.S. Pat. No. 3,795,972, issued Mar. 5, 1974 to O. Napolitano, G. P. Pasternack and B. R. Saltzberg. In this system the redundant clock outputs called the master and standby are derived from phase locked oscillators which are both phase locked to the same incoming source. The problems and weaknesses of the system of this patent is described in U.S. Pat. No. 4,019,143 issued May 10, 1976, issued to Fallon et al.
A redundant clock system for providing bit and frame clock signals is disclosed in U.S. Pat. No. 4,019,143, issued May 10, 1977 to Fallon et al. Described there is a prior art redundant timing system in which a standby clock output is phase locked to a master clock output. The weakness of this design, is that a phase discontinuity can occur during switchover because of a slow response of the master and standby phase lock loop circuitry while attempting to track a master clock reference that is malfunctioning.
The problem of phase discontinuity which occurs when switching of the clock outputs is due to a master clock malfunction causing the master clock to drift is alleged to be overcome in U.S. Pat. No. 4,019,143 of Fallon et al. However, this design also has problems of its own. The design involves three clock signals at three different frequencies, 2.048 MHZ, 512 KHZ and 8 KHZ. Due to the large amount of combinational and sequential logic used in the design, reliability is reduced and susceptible to noise interference is increased. The phase and duty factor correction precision is not defined, and there is no indication of intended use in redundant timing bus applications when two clock generators are used. The great amount of logic circuitry required by each of the redundant clock generators results in propagation delays of the numerous circuit elements which render precision tracking difficult to achieve. Also, the ability to overcome or minimize phase discontinuity between the two output busses, in order to prevent system timing errors during switchover, may not be possible with this design.